Flip-Flop Viva Questions

Flip-Flop Viva Questions

Flip-Flop Viva Questions, Viva Questions on Flip-Flop, Short Questions on Flip-Flop, Digital Electronics Viva Questions, Engineering Viva Questions, Combinational Circuit Viva Questions, JK Flip-Flop Viva Questions, SR Flip-Flop Viva Questions, Latch Viva Questions, Master-Slave Flip-Flop Viva Questions, Clocked Flip-Flop Viva Questions

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Short Questions and Answers

Q.1. Distinguish between combinational and sequential switching circuits.

Ans. Basically, switching circuits may be combinational switching circuits or sequential switching circuits. Combinational switching circuits are those whose output levels at any instant of time are dependent only on the levels present at the inputs at that time. Any prior input level conditions have no effect on the present outputs because combinational logic circuits have no memory.

On the other hand, sequential switching circuits are those whose output levels at any instant of time are dependent not only on the levels present at the inputs at that time but also on the prior input level conditions. It means that sequential circuits have memory. Sequential circuits are thus made of combinational circuits and memory elements.

Q.2. What do you mean by the stable state?

Ans. A stable state is a state in which the circuit can remain permanently. Only when an external signal is applied, it will change the state.

Q.3. What is a flip-flop?

Ans. A flip-flop is the basic memory element used to store one bit of information. It can store a 0 or a 1. The name flip-flop is because this circuit shifts back and forth between its two stable states upon application of proper inputs. Or we can say a flip-flop is a simple logic circuit.

Q.4. How many flip-flops are required for storing n bits of information?

Ans. n flip-flops are required for storing n bits of information. One flip-flop is required for every bit.

Q.5. A flip-flop is known more formally as what? How many stable states does it have?

Ans. A flip-flop is known more formally as a bistable multivibrator. It has two stable states.

Q.6. What is the flip-flop’s memory characteristic?

Ans. A flip-flop input has to be pulsed momentarily to cause a change in the flip-flop output, and the output will remain in that new state even after the input pulse has been removed. This is the flip-flop’s memory characteristic.

Q.7. What are the applications of flip-flops?

Ans. Flip-flops have innumerable applications. They are used for data storage, transfer of data, counting, frequency division, parallel-to-serial, serial-to-parallel data conversion, etc.

Q.8. What do you mean by a latch? Why that name?

Ans. An unclocked flip-flop is called a latch. This name is because the output of the unclocked flip-flop latches on to a 1 or a 0 immediately after the input is applied.

Q.9. What is an asynchronous latch?

Ans. Non-gated latches are called asynchronous latches. Here no clock signals are applied and the output latches onto a 0 or a 1 asynchronously any time proper inputs are applied.

Q.10. What is an asynchronous latch?

Ans. Clocked latches are called gated or synchronous latches. Here clock signals are applied and the output latches onto a 0 or a 1 only if the inputs are applied synchronously along with the clock.

Q.11. How do you build a latch using universal gates?

Ans. A latch may be built by using two cross-coupled NOR gates or NAND gates. By using cross-coupled NOR gates an active-HIGH SR latch can be built and by using cross-coupled NAND gates an active-LOW SR latch can be built.

Q.12. What are an active-HIGH latch and an active-low latch?

Ans. An active-HIGH latch is one in which the inputs are normally resting in the low state and one of them will be pulsed high whenever we want to change the latch outputs.

An active-LOW latch is one in which the inputs are normally resting in the high state and one of them will be pulsed low whenever we want to change the latch outputs.

Q.13. Distinguish between synchronous and asynchronous latches.

Ans. Synchronous latches are latches that respond to their inputs only when the clock is present.

Asynchronous latches are latches that respond to their inputs the moment the inputs are applied. No clock signal is present.

Q.14. What is the normal resting state of SET and CLEAR inputs in a NAND gate SR latch? What is the active state of each input?

Ans. The normal resting state of SET and CLEAR inputs in a NAND gate SR latch is both the inputs are high. The active state of each input is when the input is low.

Q.15. What is the normal resting state of SET and CLEAR inputs in a NOR gate SR latch? What is the active state of each input?

Ans. The normal resting state of SET and CLEAR inputs in a NOR gate SR latch is when both the inputs are low. The active state of each input is when the input is high.

Q.16. What is meant by clocked flip-flop?

Ans. A clocked flip-flop is a flip-flop whose state changes occur (according to the data inputs) only when a clock pulse is present.

Q.17. Name the two types of inputs that a clocked flip-flop has.

Ans. The two types of inputs that a clocked flip-flop has are (a) control inputs and (b) enable input which may be a clock.

Q.18. Why is a gated D latch called a transparent latch?

Ans. A gated D latch is called a transparent latch because the Q output follows the D input when ENABLE is high, i.e. when EN is high, a low D input makes Q low, i.e. resets the flip-flop and a high D makes Q high, i.e. sets the flip-flop.

Q.19. What are the two types of flip-flops?

Ans. The two types of flip-flops are (a) level-triggered flip-flops and (b) edge-triggered flip-flops.

Q.20. Distinguish between level-triggered flip flops and edge-triggered flip flops.

Ans. The level-triggered flip-flops are those which respond to changes in inputs when the clock is high. The edge-triggered flip-flops are those which respond only to inputs present at the transition of the clock pulse.

Q.21. What are the various methods used for triggering flip-flops?

Ans. The various methods used for triggering flip-flops are as follows:

1. Level triggering
2. Pulse triggering
3. Positive edge triggering
4. Negative edge triggering

Q.22. What is dynamic triggering?

Ans. Dynamic triggering is the other name for edge triggering.

Q.23. Which is the most versatile and most widely used of all the flip-flops?

Ans. The JK flip-flop is the most versatile and most widely used of all the flip-flops.

Q.24. Explain the operation of a JK flip-flop.

Ans.

1. When J = K = 0, the outputs are not affected by the clock pulse.
2. When J = K = 1, the outputs get complimented when a clock pulse is applied.
3. J =1, K = 0 sets the flip-flop when clock is applied.
4. J = 0, K = 1 resets the flip-flop when clock is applied.

Q.25. List the different types of latches and flip-flops?

Ans. The different types of latches are: active-low SR latch, active-high SR latch, and D latch – all of these are unclocked or non-gated latches. Gated latches called flip-flops are gated SR latches and gated D latches. The flip-flops are S-R flip-flop, D flip-flop, J-K flip-flop, and T flip-flops which are edge-triggered.

Q.26. Which flip-flops are not widely available commercially?

Ans. The T flip-flops are not widely available as commercial units.

Q.27. Explain the operation of an SR flip-flop.

Ans.

1. When S = R = 0, the outputs are not affected by the clock pulse.
2. When S = R = 1, the output is ambiguous. It is invalid.
3. S =1, R = 0 sets the flip-flop when clock is applied.
4. S = 0, R = 1 resets the flip-flop when clock is applied.

Q.28. How does a J-K flip-flop differ from an S-R flip-flop in its operation? What is its advantage over an S-R flip-flop?

Ans. In an S-R flip-flop, the condition both inputs are equal to 1 is invalid, whereas in a J-K flip-flop both inputs are equal to 1 resulting in toggle mode. The advantage is in ripple counters, the flip-flops are to be in toggle mode.

Q.29. What is the main difference between a gated latch and an edge-triggered flip-flop?

Ans. The gated latches are called level-triggered flip-flops. They respond to the inputs when the clock is high. The edge-triggered flip-flops respond to the inputs only at the transition of the clock.

Q.30. Which flip-flop is preferred for counting? Which one is preferred for data transfer?

Ans. The J-K flip-flop is preferred for counting and the D flip-flop is preferred for data transfer.

Q.31. What do you mean by toggling?

Ans. Toggling means changing the output to the opposite state each time a clock pulse is applied.

Q.32. What are PRESET and CLEAR inputs?

Ans. PRESET and CLEAR inputs are asynchronous inputs. They override all other inputs. They are also called DC SET, DC RESET or DC CLEAR, Direct SET (S_D), and direct RESET (R_D). The PRESET input forces the output Q to 1 and CLEAR input forces the Q output to 0.

Q.33. What do (a) a triangle, (b) a bubble and a triangle, and (c) no symbol at the clock terminal of a flip-flop indicate?

Ans. A triangle at the clock input terminal of a flip-flop indicates that it is a positive edge-triggered flip-flop. A bubble and a triangle at the clock input terminal of a flip-flop indicate that it is a negative edge-triggered flip-flop. No symbol at the clock input terminal of a flip-flop indicates that it is a level-triggered flip-flop.

Q.34. Why are asynchronous inputs called overriding inputs?

Ans. Asynchronous inputs are called overriding inputs because they override the control inputs, i.e. in the presence of override inputs no other inputs are effective.

Q.35. What do you mean by clock skew?

Ans. The clock signal which is applied simultaneously to all the flip-flops in a synchronous system may undergo varying degrees of delay caused by wiring between the components and arrive at the CLK inputs of different flip-flops at different times. This delay is called clock skew.

Q.36. What do you mean by time race?

Ans. If the clock skew is minimal, a flip-flop may get clocked before it receives a new input (derived from the output of another clocked flip-flop). On the other hand, if the clock pulse is delayed significantly, the inputs to a flip-flop may have changed before the clock pulse arrives. In these situations, we have a kind of race between the two competing signals that are attempting to accomplish opposite effects. This is called the time race.

Q.37. What is meant by race around condition in flip-flops?

Ans. In a JK flip-flop when J = K = 1, and the clock is applied, the outputs go on complementing every ΔT (delay time of flip-flop) as long as the clock is present. Therefore, the output at the end of the clock pulse is ambiguous. This condition is known as the race around condition.

Q.38. Define the following terms as applied to flip-flops.

1. Set-up time
2. Hold time
3. Propagation delay time
4. Maximum clock frequency
5.  Power dissipation

Ans.

Set-up time: The set-up time (t_s) is the minimum time for which the control levels need to be maintained constantly on the input terminals of the flip-flop prior to the arrival of the triggering edge of the clock pulse in order to enable the flip-flop to respond reliably.

Hold time: The hold time (t_h) is the minimum time for which the control signals need to be maintained constant at the input terminals of the flip-flop after the arrival of the triggering edge of the clock pulse, in order to enable the flip-flop to respond reliably.

Propagation delay time: The time interval between the time of application of the triggering edge of asynchronous inputs and the time at which the output actually makes a transition is called the propagation delay time of the flip-flop.

Maximum clock frequency: The maximum clock frequency (f_max) is the highest frequency at which a flip-flop can be reliably triggered.

Power dissipation: The power dissipation of a flip-flop is the total power consumption of the device. It is equal to the product of the supply voltage (V_CC) and the current (I_CC) drawn from the supply by it. P = V_CC I_CC

Q.39. How do you convert one type of flip-flop into another?

Ans. To convert one type of flip-flop into another type, a combinational circuit is designed such that if the inputs of the required flip-flop (along with the outputs of the actual flip-flop if required) are fed as inputs to the combinational circuit and the output of the combinational circuit is connected to the inputs of the actual flip-flop, then the output of the actual flip-flop is the output of the required flip-flop.

Q.40. What is a master-slave flip-flop?

Ans. A master-slave flip-flop is a cascade of two flip-flops in which the first one responds to the data inputs when the clock is high, whereas the second one responds to the outputs of the first one when the clock is low. Thus the final outputs change only when the clock is low when the data inputs are not effective.

Thus the race around condition gets eliminated in this. The first flip-flop is known as the master and the second as the slave.

Q.41. Why are master-slave flip-flops called pulse-triggered flip-flops?

Ans. Master-slave flip-flops are called pulse-triggered flip-flops because the length of the time required for its output to change state equals the width of one (clock) pulse.

Q.42. Differentiate between edge-triggered and master-slave flip-flops.

Ans. In edge-triggered flip-flops, only a positive or negative edge is required for triggering, whereas in the case of master-slave flip-flops both a positive and a negative edge are required for triggering.

Q.43. What are data lock-out flip-flops?

Ans. Data lock-out flip-flops are nothing but master-slave flip-flops in which the master is an edge-triggered flip-flop.

Q.44. What is a trigger?

Ans. A momentary change of signal level and return to the initial level is referred to as a trigger.

Q.45. What do you mean by excitations?

Ans. The inputs to the flip-flops are called excitations.

Q.46. What is an excitation table?

Ans. An excitation table is a table that lists the inputs required to be applied to the flip-flop to take it from the given present state to the required next state.